BIT PRTIM1=0 ;DISABLE POWER REDUCTION
wr16=1ffh
[TCNT1H]=r17 ;tmp register
[TCNT1L]=R16
OCR1AH ;TEMP
OCR1AL
ICR1H ;TEMP
ICR1L
ICR1,OCR1A,OCR1B,OCR1C
ICR3,OCR3A,OCR3B,OCR3C

[WGM1 BITS0-3]=
0;normal mode 0->0ffffh produce overflow inT
4;CTC MODE 0->OCR1A
12;0->ICR1
5;0->0ffh
6;0->1ffh
7;0->2ffh
8;0->ICRN->0
9;0->OCRNA->0
14;0->ICR1 PWM PRODUCE COMPARE INTERRUPT
15;0->OCR1A PWM double bufered
TCCR1A ;1a1,1a0,1b1,1b0,1c1,1c0,WGM1,WGM0
TCCR3A
;non pwm 1A1,1A0 = no output,togle,clear,set (on compare match)
;
TCCR1B
	bit 7 ICNC enable noise canceller
	bit 6 ICES capture edge: falling,rising
	bit 5 reserved
	bit 4 WGM3
	bit 3 WGM2
	bits 0-2 CLOCK=STOP,1,1/8,1/64,1/256,1/1024,ext,ext
TCCR1C ;FORCE COMPARE A,B,C,,,,,
TIMSK1 ;,,ICIE1,,OCIE1C,OCIE1B,OCIE1A,TOIE1 ;INTERRUPT ENABLE
TIFR1  ;BIT A 1 CUANDO OCURRE ALGO BIT A 0 AL EJECUTAR LA INTERRUPCION
;Timer counter 4
port direction bits on the port must be set before output is enabled
OCR4A OCR4B OCR4D  value to compare with TCNT4
OCR4C top,minimum value=3
OCR4X registers are double bufered in pwm modes
TCNT4 counter value
TC4H temp register for bits 10-8
TCCR4A
	bits 6-7 comparator A mode
	normal mode:disconected,togle,clear,set
	in non normal modes complementary output is used in mode 1
	fast pwm :disconected,clear,clear,set  ;bit togle at bottom
	phase and freq correct:disconected,clear,clear,set ;bit togle when down counting
	bits 4-5 comparator B mode
	bit 2-3 only active in now pwm modes
	force compare match B-A
	bit 0-1 enable pwm B-A
TCCR4B
	bit 7 pwm inversion mode
	bit 6 prescaler reset,cleared by hardware
	bits 4-5 dead time prescaler divide by :1,2,4,8
	bits 0-3 prescaler divide: stop,1,2,4,8,16,.....,16384

TCCR4C  bits 4-7 shadow bits 4-7 of TCC4RA
	bits 2-3 comparator D mode
	bit 1 force compare D
	bit 0 enable pwm D
TCCR4D
	bit 7 fp (fault protection) interrupt enable
	bt 6 enable fp mode
	bit 5 enable fp noise canceler
	bit 4 fp edge :falling,rising
	bit 3 use ACO to signal fp
	bit 2 fp interrupt flag
	bit 0-1 pwm: fast,phase,pwm6 single,pwm6 dual
TCCR4E
	bit 7 register update lock
		compare registers are not updated if this bit is set
	bit 6 enhanced mode
		when set ,the compare registers have one more bit
		lsb selects the clock edge of the compare match
	bits 0-5 output compare override for pwm6
TIMSK4  bits 5-7 compare B-A-D interrupt enable
	bit2     overflow interrupt enable
TIFR4   interrupts flags
DT4     bits 4-7 dead time1
	bits 0-3 dead time2


;system clock
CLKPR=80H ;enable change
CLKPR=0->8 ;1->1/256
;SLEEP
SMCR=1+2*0->7 ;IDLE,ADC NOISE REDUCTION,POWER DOWN,POWER SAVE,RES,RES,STANDBY,EXT STANDBY
sleep
;IDLE=STOP CPU
;NOISE REDUCTION=STOP CPU,IO
;POWER DOWN=STOP ALL CLOCKS BUT WATCHDOG
;STANDBY=POWER DOWN WITH OSCILATOR RUNING,WAKES UP IN 6 CLOCKS

;POWER
PRR0    ;SETING BITS TO ONE POWER OFF
	bit 7 PRTWI
	bit 6 res
	bit 5 PRTIM0
	bit 4 res
	bit 3 PRTIM1
	bit 2 PRSPI
	bit 1 res
	bit 0 PRADC
PRR1    bit 7 PRUSB
	bit 5-6 res
	bit 4 PRTIM4
	bit 3 PRTIM3
	bits 1-2 res
	bit 0 PRUSART1


;usb
;in-out is relative to the usb host (computer)
;1.25Kb sram
;832 bytes dpram for endpoint memory allocation
;endpoint 0 max 64 bytes one bank
;endpoint 1 max 256 bytes
;endpoint 2-6 max 64 bytes
;interrupts flags need to be cleared by soft ,else interrupts are disabled
UHWCON bit 0 set to enable pad regulator
USBCON
	bit 7 USBE set to enable usb controller ,clear to reset ,disable and stop clocks
	bit 6 res
	bit 5 FRZCLK set to disable clock clear to enable,set by hardware after usb enable
	bit 4 OTGPADE set to enable vbus pad,clear to disable
	bits 1-3 res
	bit 0 VBUSTE enable vbus transition int

USBSTA bits 2-7 res
	bit  1=1 (otg id pin for compatibility)
	bit 0 vbus state

USBINT bits 1-7 res
	bit 0 VBUSTI vbus transition interrupt flag,cleared by soft

UDCON
	bit 4-7 res
	bit 3 RSTCPU
	bit 2 LSM 1=select low speed mode
	bit 1 RMWKUP
	bit 0 DETACH set to disconnect clear to reconnect


UDINT   ;ints flags cleared by soft
UDIEN   ;enable ints
	bit 7 res
	bit 6 UPRSME
	bit 5 EORSME
	bit 4 WAKEUPE
	bit 3 EORSTE ;end of reset ,enpoint config&ints needs to be reprogrammed
	bit 2 SOFE
	bit 1 res
	bit 0 SUSPE ;suspe and wakeupe are complementary and used alternatively

UDADDR  bit 7 addres enable
	bits 0-6 usb adress

UDFNUMH-UDFNUML bits 0-10 frame number

UDMFN   bits 5-7 res
	bit 4 FNCERR frame crc error flag
	bits 0-3 res


UENUM   bits 3-7res
	bits 0-2 selects the endpoint accessed by the cpu

UERST   bit 7 res
	bits 0-6 reset the corresponding endpoint fifo set by hardware,clear by soft to complete the reset
	and start using the fifo.
UECONX
	bits 6-7 res
	bit 5 STALLRQ
	bit 4 STALLRQC
	bit 3 RSTDT reset data togle bit
	bits 1-2 res
	bit 0 EPEN endpoint enable bit


UECFG0X
	bits 6-7 EPTYPE endpoint type: control,isocronous,bulk,interrupt
	bits 1-5 res
	bit 0 EPDIR 0= control or out endpoint,1=in endpoint
UECFG1X
	bit 7 res
	bits 4-6 endpoint mem size 8,16,32,64,128,256,512,res
	bit 3 res
	bits 2 one bank,double bank
	bit 1 set to 1 to allocate memory set to 0 to free memory
	bit 0 res
UESTA0X
	bit 7 CFGOK set to 1 if memory allocation was ok
	bit 6 OVERFI overflow interrupt in isocronous endpoint ,cleared by soft
	bit 5 UNDERFI flow interrupt error,cleared by soft
	bits 4-3 res
	bit 2 data togle
	bits 0-1 NBUSYBK number of busy (filled) banks
UESTA1X ;readonly
	bits 7-3 res
	bit 2 CTRLDIR set by hardware after a setup packet,gives direction of next packet
		1=in 0=out
	bits 0-1 CURRBK current bank : bank0,bank1,reserved (not for control endpoint)
UEINTX
	bit 7 FIFOCON fifo contro bit
	set by hardware
	clear to send/free current bank and switch to next bank
	bit 6 NAKINI nak in interrupt flag
	bit 5 RWAL (not for control endpoint)
	set to 1 if current bank can be read/write
	bit 4 NAKOUTI nak out interrupt flag
	bit 3 RKSTPI received setup interrupt flag
	bit 2 RXOUTI received out packet interrupt flag
	bit 1 STALLEDI interrupt flag,indicates a stall send or error
	bit 0 TXINI interrupt flag,indicates that current bank can be filled
UEIENX (INTERRUPT ENABLE)
	bit 7 FLERRE flow error
	bit 6 NAKINE
	bit 5 res
	bit 4 NAKOUTE
	bit 3 RXSTPE
	bit 2 RXOUTE
	bit 1 STALLEDE
	bit 0 TXINE
UEDATX

UEBCHX
	bits 7-3 res
	bits 0-2 BYCT bits 8-10 of fifo byte count
UEBCLX  bits 0-7 of fifo byte count

UEINT
	bit 7 reserved
	bits 0-6 interrupt flag for the corresponding endpoint
		clear by hardware

;usb setup
;power on
OTGPADE=1       ;power on pads
 ;configure pll
;enable pll
;wait pll lock
;enable usb
;configure usb speed,endp,config
;wait for vbus information connection
;attach usb device


;power off
detach,disable usb,disable pll,disable regulator
;endpoint activation
select endp,activate endp,configure (direction,type,endpoint siz,bank)
if CFGOK=1 OK else error

;address setup
;after power up adress 0 is used
;host sends a set address command
;firmware stores addres in UADD
;firmware sends a in command of 0 bytes and then sets the ADDEN


;PLL
PLLCSR
	bits 5-7 res
	bit 4 crystal is 8,16mhz ;set before enable
	bits 2-3 res
	bit 1 pll enable
	bit 0 pll lock ,some mseconds after pll enable the pll lock is set (ready)
PLLFRQ
	bit 7 set to 1 to use the internal 8mhz rc clock ,allows usb 1.5mbits
	bit 6 PLLUSB usb postcaler 1 to divide by 2 the 96Mhz signal
		0 if freq is 48Mhz
	bit 4-5 PLLTM1 timer postcaler disconected,1,1.5,2
	bits 0-3 PLL frequency res,res,32,40,48,56,64,72,80,88,96,res...
;recomended to use 5v 96Mhz divided by 1.5 for timer and 2 for usb

;ADC
ADMUX
	bits 6-7 voltage reference: aref(input),avcc,reserved,aref(2.56v)
	bit 5    1=result is left ajusted ,is enought to read adch.
	bits 0-4 chanel select bit 5 is in ADCSRB
0       adc0
	adc1
4       adc4
	adc5
	adc6
	adc7
9       adc1,adc0,10x (+,-,gain)
11      adc1,adc0,200x
10h     adc0,adc1,1x
14h-17h adc4-7,adc1,1x
1eh     1.1v band gap
1fh     0v
20h-25h adc8-13
26h     adc1,adc0,40x
27h     temperature sensor
28h-3fh adc4-7,adc0-1,10x-40x-200x (28h=adc4,adc0,10x)(30h=adc4,adc0,40x)(3fh=adc7,adc1,200x)

ADCSRA
	bit 7 enable bit
	bit 6 start conversion
	bit 5 auto triger enable
	bit 4 interrupt flag ,cleared by hardware,or writing a one
	bit 3 interrup enable
	bits 0-2 division factor betwen xtal and adc clock:2,2,4,8,16,32,64,128
ADCSRB
	bit 7 enable high speed mode
	bit 6 analog comparator multiplex enable bit
	bit 5 chanel select
	bit 4 reserved
	bits 0-3 auto triger source
0       free runing mode
	;interrupt must be enabled
1       analog comparator
2       external int 0
3       timer 0 compare match
4       timer 0 overflow
5       timer 1 compare match b
6       timer 1 overflow
7       timer 1 capture event
8       timer 4 overflow
9-11    timer 4 compare match a b d

DIR0 digital input disable adc0-7
DIR2 digital input disable adc8-13
	write one to reduce power comsumption if only analog input is used
ADCH ADCL 10 bits result

;ANALOG COMPARATOR
ACSR
	bit 7 analog comparator disable
	bit 6 +input: ain0,bandgap
	bit 5 analog comparator output
	bit 4 interrupt flag ,cleared by hardware
	bit 3 interrupt enable
	bit 2 input capture enable on timer 1
	bits 0-1 interrupt mode:togle,reserved,falling,rising

MUX0-2  -input: adc0,adc1,,,adc4,adc5,adc6,adc7
;JTAG
OCDR
MCUCR   bit 7 JTAG DISABLE ;this bit must be write twice in 4 clks
	bit 4 pull up disable
MCUSR   bit 4 JTAG reset flag

;EEPROM
;eeprom can not be programmed during flash write(SPMCSR.SEFLPRGEN=1)
EEARH
EEARL adress registers
EEDR  data register
EECR  control register
	bit 4-5 programing mode: erase and write(3.4ms),erase only (1.8ms),write only(1.8ms),reserved
	bit 3  ready interrupt enable
	bit 2  master programing enable  autoclear in 4 clks
	bit 1  programing enable        sets to zero weh ready for next byte
	bit 0  read enable
;write procedure:
	wait until EECR.1=0
	EEAR=new address EEDR=data
	cli EECR=4 (o sbi EECR,2) EECR=6 sti
;read procedure
	wait until EECR.1=0
	EEAR=new address
	EECR=1 data=EEDR

